The present invention relates to semiconductor memory devices, and more particularly to an embedded dynamic random access memory (DRAM) cell array that is scalable to groundrules that are below about 55 nm, without succumbing to a dynamic buried-strap to buried-strap leakage mechanism that is caused by the periodic cycling of an adjacent wordline. A method of forming such an ultra-low scalable memory cell array is also provided herein.
As conventional vertical DRAM cells are scaled below a design groundrule of about 110 nm, encroachment of the buried-strap region upon the sidewall of the adjacent storage trench cuts-off the path in which holes can flow into and out of the portion of the P-well above the buried-strap region.
Simulation has demonstrated that floating-well effects limit the scalability of prior art vertical DRAM memory arrays to a minimum distance of about 90 nm between adjacent storage trenches. A number of dynamic leakage mechanisms limiting the scalability of conventional vertical DRAM memory cells have been identified and quantified. Included in the dynamic leakage mechanisms are: (1) Floating-well bitline disturb (FWBD), (2) Transient drain induced barrier lowering (TDIBL), and (3) Adjacent wordline induced punchthrough (AWIPT).
The onset of serious charge loss due to each mechanism occurs at approximately 90 nm end of process deep trench (DT) to deep trench (DT) spacing. Thus, scalability of conventional vertical DRAM memory cells beyond about 110 nm is expected to be limited by floating-well effects.
An illustration of a dominant floating-well dynamic leakage mechanism that limits scalability of prior art vertical DRAM memory arrays is shown in FIG. 1. Specifically, at a time indicated by point A of FIG. 1 and during a long period of about 5-100 ms of repeated writing of a xe2x80x9c1xe2x80x9d to other memory cells on the bitline, the P-well of an unselected cell storing a xe2x80x9c1xe2x80x9d may leak up towards bitline voltage (Vblh), as the exiting of holes is restricted by parasitic JFET. Leakage depends on the degree of well isolation caused by pinchoff from expansion of the storage node depletion region. In an extreme case, the buried-strap region may come in contact with the adjacent deep trench capacitor. Moreover, the hole current through the pinchoff region must keep up with the leakage to avoid a pseudo xe2x80x9cFloating-Body Effectxe2x80x9d.
Insofar as time interval B-C is concerned, the N+ bitline diffusion to P-well barrier is lowered by a downward swing of Vblh. Electrons emitted from the bitline diffusion region are collected by the storage node resulting in the formation of a parasitic bipolar transistor, Qw, (PWint is a floating base) within the memory cell array.
For aggressively scaled vertical metal oxide semiconductor field effect transistors (MOSFETs) in prior art vertical DRAM memory cells, the depletion region from the storage node diffusion (i.e., buried-strap outdiffusion) encroaches upon the sidewall of the adjacent storage trench, which results in dynamic charge loss from the storage capacitor as the bitline of an unselected device is cycled. This charge loss mechanism is identical to that published in xe2x80x9cFloating-Body Concerns for SOI Dynamic Random Access Memory (DRAM)xe2x80x9d, Proceedings, 1996 IEEE International SOI Conference, Jack Mandelman, et al. pp. 1367-137, October 1996.
An illustration of the storage capacitor voltage vs. the voltage in the portion of the P-well isolated by the depletion region from the buried-strap outdiffusion, as the bitline is cycled, is shown in FIG. 2. When the bitline is held at Vblh, the isolated portion of the P-well (PWint) leaks up towards the voltage of the adjacent diffusions. With subsequent cycling of the bitline between 0.0 and Vblh, the dynamic charge loss mechanism results in charge pumping which discharges the storage capacitor. Between data refresh, greater than 106 bitline cycles are possible, which is sufficient to discharge the storage capacitor.
Another problem with prior art DRAM cells is backgating which causes back side leakage that is gated by the adjacent wordline in the DRAM CELL. An illustration of the backside leakage problem is shown, for example, in FIG. 3.
A still other problem with prior art DRAM cells, which contain more than one cell within a common active semiconductor region, is that the scalability of such DRAM cells eventually succumbs to a dynamic buried-strap to buried-strap leakage mechanism that is caused by the periodic cyclic of an adjacent wordline. That is, the scaling of the prior art DRAM cells to groundrules of less than about 90 nm, especially less than about 55 nm, may result in the coupling of the diffusion regions that may cause leakage in the DRAM cell.
In view of the above drawbacks with prior art memory cells, there is a need to provide a new and improved memory cell array which is substantially immune to floating- well and backgating problems, yet is capable of being scaled below 90 nm, especially less than about 55 nm, without succumbing to leakage caused by coupling of buried-strap diffusion regions.
One object of the present invention is to provide a memory cell array that substantially eliminates floating-well effects that are typically present in prior art memory cells.
Another object of the present invention is to provide a memory cell array that substantially eliminates the prior art backgating problem due to an adjacent wordline.
A further object of the present invention is to provide a memory cell array that is scalable below a minimum feature size of about 55 nm, without succumbing to a dynamic buried-strap to buried-strap leakage mechanism that is caused by the periodic cycling of an adjacent wordline.
A yet further object of the present invention is to provide a memory cell array wherein the channel doping of the cell is reduced, without compromising cell to cell isolation.
These and other objects and advantages are achieved in the present invention by providing a memory cell array that includes, among other components, self- aligned punch through stop regions that do not excessively impinge upon the buried- strap regions. The inventive self-aligned punch through stop regions comprise a locally high concentration of punch through stop dopant such as boron that is substantially confined to the central region between adjacent strap regions of deep trenches.
In one aspect of the present invention, a method of fabricating a memory cell array that includes at least the self-aligned punch through stop regions is provided. The inventive method includes the steps of:
forming double-gated vertical MOSFETs in a plurality of deep trenches that are present in a Si-containing substrate, wherein said double-gated vertical MOSFETs include at least two gates on opposing sidewalls, exposed gate conductors and a buried- strap region;
forming wordlines overlaying said double-gated vertical MOSFETs and in contact with said exposed gate conductors;
forming bitlines on said Si-containing substrate that are orthogonal to said wordlines;
etching isolation trench regions into portions of said Si-containing substrate that are adjacent to rows of deep trenches using said wordlines and bitlines as etch masks, said isolation trench regions having a depth that is deeper than abutting bitline diffusion regions; and
forming punch through stop regions into said etched isolation trench regions using said bitlines and wordlines as implant masks, said punch through stop regions are capable of isolating adjacent buried straps from each other and are centrally located about the deep trenches in areas adjacent to said gates, wherein neighboring punch through stop regions in the wordline direction overlap each other under the bitlines.
After the punch through stop regions are formed, the etched isolation trench regions are filled with an oxide material and planarized.
Another aspect of the present invention relates to a memory cell that includes at least self-aligned punch through stop regions having overlapped areas beneath the bitlines. Specifically, the inventive memory cell array comprises:
a plurality of memory cells located in an array portion of a Si-containing substrate which are arranged in rows and columns, each memory cell including a double- gated vertical metal oxide semiconductor field effect transistor (MOSFET) having exposed gate conductor regions and two gates formed on opposing sidewalls of said MOSFETs, wherein one of the opposing sidewalls also includes a confined buried-strap region;
a plurality of wordlines overlaying said double-gated vertical MOSFETs and in contact with said exposed gate conductor regions, said wordlines being arranged in said column direction;
a plurality of bitlines that are orthogonal to said wordlines;
trench isolation regions located adjacent to said rows of memory cells, wherein said trench isolation regions have a depth that is deeper than abutting bitline diffusion regions; and
a plurality of punch through stop regions located in said Si-containing substrate, wherein said plurality of punch through stop regions in said column direction overlap each other under said bitlines and serve to electrically isolate adjacent buried-strap regions from each other.